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Article – Journal of Nanoscience and Technology

Journal of Nanoscience and Technology, Volume 4,Issue 5,2018 Pages 575-579


Design and Analysis of CMOS and CNTFET based Ternary Operators for Scrambling
Gudala Konica*, Sreenivasulu Mamilla

https://doi.org/10.30799/jnst.187.18040530

As silicon technology scales down, it is a dominant choice to have high-performance digital circuits. As researchers investigated for high-performance digital circuits for future generations, Carbon Nanotube Field Effect Transistors (CNTFETs) is considered as the most promising technology due to their excellent current driving capability and proved to be an alternative to conventional CMOS technology. A CNTFET based energy efficient ternary operators are proposed for scrambling applications. The transistor-level implementations of operators namely Scrambling Operator1 (SOP1), Scrambling Operator2 (SOP2) and SUM operators are simulated with CMOS and CNTFET in 32 nm technology at 0.9 V supply voltage using Synopsys HSPICE. The performance metrics like Power, Delay and Power-delay product (PDP) are measured and a comparative analysis for CNTFET and CMOS technologies is carried out. The results demonstrate that CNTFET designs have better-optimized results in power, energy consumption, and reduced transistor count.



Keywords: CNTFET; Scrambling; Ternary Logic; Ternary Operator; MVL;